Modern semiconductor fabrication involves numerous steps including photolithography, material deposition, and etching to form a plurality of individual semiconductor devices or integrated circuit chips (dice) on a single semiconductor silicon wafer. Typical semiconductor wafers produced today may be at least about 6 inches or more in diameter, with a 12 inch diameter wafer being one common size. Some of the individual chips formed on the wafer, however, may have defects due to variances and problems that may arise during the intricate semiconductor fabrication process. Prior to wafer dicing wherein the individual integrated circuit chips (dies) are separated from the semiconductor wafer, electrical performance and reliability tests are performed on a plurality of chips simultaneously by energizing them for a predetermined period of time (i.e., wafer level burn-in testing). These tests may typically include LVS (layout versus schematic) verification, IDDq testing, etc. The resulting electrical signals generated from each chip or DUT (device under test) are captured and analyzed by automatic test equipment (ATE) having test circuitry to determine if a chip has a defect.
To facilitate wafer level burn-in testing and electrical signal capture from numerous chips on the wafer at the same time, DUT boards or probe cards as they are commonly known in the art are used. Probe cards are essentially printed circuit boards (PCBs) that contain a plurality of metallic electrical probes that mate with a plurality of corresponding electrical contacts or terminal formed on the wafer for the semiconductor chips. Each chip or die has a plurality of contacts or terminals itself which must each be accessed for testing. A typical wafer level test will therefore require that electrical connection be made between well over 1,000 chip contacts or terminals and the ATE test circuitry. Accordingly, precisely aligning the multitude of probe card contacts with chip contacts on the wafer and forming sound electrical connections is important for conducting accurate wafer level testing. Probe cards are typically mounted in the ATE and serve as an interface between the chips or DUTs and the test head of the ATE.
It is preferable to test all of the chips on an entire semiconductor wafer at one time in parallel for efficiency and to minimize chip production time. Ideally, therefore, it is desirable to move the probe card (and testing probes thereon) into physical engagement or contact with the surface of the wafer (“touch down”) only once and to test the entire wafer at one time. To accomplish this requires that precise and complete electrical contact be established during the initial touch down between all of the probe card contacts and corresponding chip contacts. However, limitations with existing probe cards and probes sometimes may prevent proper mating of contacts on the wafer and probe card on the first try. This requires multiple engagements or touch downs between the probe card and wafer in order to successfully mate all of the probe card and chip contacts, which reduces testing efficiency and increases chip production time and costs.
Referring to FIG. 1A, one type of known probe card uses a plurality of electrical probe contacts in the form of cantilevered metallic curved spring fingers that mate with corresponding contacts on the wafer to establish sufficient stylus or contact pressure therebetween for accurate testing. The flexible fingers are relatively thin and have a fixed end mounted on a rigid ceramic substrate which is then coupled to a printed circuit board (PCB). The contact fingers are oriented generally parallel to the surface of the probe card where attached to the card and then gradually curve upwards towards vertical near the free ends of the fingers that physically engage the electrical contacts on the wafer. The fingers will flex and tend towards straightening out when compressed against the wafer contacts to absorb the contact stress resulting from forcing the probe card into engagement with the wafer. Ideally, the free ends of the fingers will all lie in the same preferably flat imaginary plane to provide proper contact or stylus pressure between the probe card fingers and chip electrical contacts on the surface of the wafer. With repetitive use and handling over time, however, the free ends of some of the fingers may become misaligned due to physical damage and thermal and mechanical fatigue. Therefore, some of fingers will not be coplanar any longer with the other fingers. While this may not be problematic for testing single dies or multiple dies on small portions of an entire wafer, non-planar probe fingers may result in inadequate contact and stylus pressure between all probe card and wafer contacts when an entire wafer and plurality of dies thereon are tested at a single time. This may prevent obtaining accurate electrical test data for all of the dies or chips on the entire wafer at once. Therefore, multiple touch downs between the probe card and wafer may therefore be required to complete wafer level burn-in testing. In addition, the non-planar probe finger problem also limits the size of the entire wafer that can be tested in a single touch down because the planar misalignment of the fingers becomes magnified as the probe card becomes increasingly larger.
Referring to FIG. 1B, another type of known probe card uses a plurality of electrical probe contacts in the form of substantially vertical metallic needles each having a fixed upper end attached to a rigid upper substrate (coupled then to a PCB) and a free floating lower end that extends through a hole in a rigid lower ceramic substrate spaced apart from the upper substrate. The floating lower end of the needle engages the chip electrical contacts or electrodes on the surface of the wafer. The needles may be shaped with a slight bulge between the ends to add some flexibility for establishing sufficient stylus pressure and to absorb the contact stress resulting from forcing the probe card into engagement with the wafer without breaking the thin needles. With repetitive use, needle co-planarity problems may develop over time similar to the spring finger type probes discussed above resulting in problems with testing all dies on an entire wafer at once. Accordingly, an improved testing probe card with electrical contacts is desired for wafer level testing.